1. Field of the Invention
The present invention relates to metal oxide semiconductor (MOS) devices and, in particular, to a trench, double diffused MOS (DMOS) transistor structure wherein the contact to the transistor's source and body is self-aligned to the trench. The self-aligned contact reduces the distance between trench edges with a resulting increase in packing density and current driving capability and decrease in on-resistance. Alternate methods of fabricating the self-aligned contact structure are also provided.
2. Discussion of the Relevant Art
For power trench DMOS transistors, the on-resistance is minimized if the source and body region can be made the same size as the trench width. While the trench width can be made as small as 1 micron or less with current integrated circuit fabrication technology, the dimension of the source and body region is governed by the size of the source and body contact opening, typically from 2 to 5 microns, and the alignment tolerance, typically larger than 1 micron, from the edge of the contact to the edge of the trench.
U.S. Pat. No. 5,316,959, issued to Kwan, et al. on May 31, 1994, discloses a trench DMOS transistor which utilizes conventional lithographic technology for fabricating a contact to the source and body of a trench DMOS device. Specifically, the Kwan et al patent discloses a process flow that requires six masking steps for fabricating a trench DMOS device structure. Three masking steps include a contact hole masking step in which portions of a boro-phosphosilicate glass (BPSG) layer overlying the trench structure are removed to form contact openings to the p+ regions and to the trench polysilicon. Thus, the Kwan et al approach suffers from the same mask alignment tolerance problems common to the prior art.
U.S. Pat. No. 5,171,705, issued to Choy on Dec. 15, 1992, discloses a high density DMOS transistor that utilizes a self-aligned structure in combination with a body contact region which overdopes the source region to minimize the number of required masking steps. The Choy structure uses dielectric spacers to eliminate the need for the contact masking step. While eliminating the contact mask, the Choy technique is not directed to a trench DMOS device.
It would be desirable to have available structure and fabrication methods for providing a self-aligned contact trench DMOS transistor.